1. Field of the Invention
Embodiments of the invention relate generally to a Serial Peripheral Interface for connecting a host device to memory devices.
2. Description of the Related Art
A serial peripheral interface bus (SPI) is a four wire serial communication interface that enables a serial data link between two devices, a master and a slave. It provides support for a low to medium bandwidth network connection between the devices supporting the SPI. Since SPI utilizes only four wires for communication, SPI has become popular for use in systems that require relatively simple IC packages.
The four wires of the SPI include of two control lines and two data lines. The control lines of the SPI include a Chip Select (CS) line and a Serial Clock (SCK) line. While more than one slave device can be connected to the master device, only one slave device may be accessed at any given time. This selection is accomplished by use of the CS line. A CS signal is outputted from the master and allows for activation and deactivation of a slave device by the master device. Every slave device requires a separate CS line for activation. Thus, if ten slave devices exist on the network, there are ten independent chip select lines, one chip select line per slave device.
The master device also provides the serial clock. The SCK is used to clock the shifting of serial data into and out of the master and slave devices. Use of this clock allows SPI architecture to operate in a master/slave full duplex mode, where data is transferred simultaneously from one device acting as a master to a second device acting as a slave.
The data lines of the SPI include a Serial Data In (SI) line and a Serial Data Out (SO) line. The SI line is a data communication line that outputs data from the master device to the slave device. The SO line is a second data communication line used to output data from the slave device to the master device. Both data lines are active only when CS is selected for the specified slave device.
SPI has been used with memory devices such as EEPROM and NOR flash memory. NOR flash memory is a popular and fairly inexpensive memory device. NOR flash memory provides full address and data buses, thereby allowing random access to any memory location. Moreover, typically in NOR flash memory, there is no need for error correction capabilities. This is because the NOR flash memory typically has good reliability without the use of error correction systems. However, a downside of NOR flash memory is that it experiences long erase and write times.
NAND flash memory has faster erase times than NOR flash memory. It also requires smaller chip area per cell than NOR flash memory, leading to greater storage density than that available in NOR flash memory. NAND flash memory also has up to ten times more endurance than conventional NOR flash memory. However, NAND flash memory typically requires some error detection and correction capabilities. Moreover, NAND flash memory does not directly allow for random data access.
Instead of being randomly accessible, like the NOR flash memory, the NAND memory array is made up of many pages of data. To access any specific data location in the array, the corresponding page associated with that data location must be accessed. The page accessed is typically read into a page cache, which can then be accessed for any specific data in the page.
Due to the differences between NOR flash memory devices and NAND flash memory devices, a SPI system configured for use with a NOR flash memory device does not accommodate a NAND flash memory device. Thus, there is a need for a SPI system configured specifically for use with a NAND flash memory device. Embodiments of the invention may be directed to one or more of the problems set forth above.